The present invention relates to a technology for controlling the reflection of a transmission signal, which is caused by branching of wirings in a memory system using memory modules, etc., and to a technology effective for application to a high-speed access-compatible memory system.
SSTL (Stub Series Terminated Transceiver Logic) has been known as a small-amplitude interface intended for a memory system. The SSTL has been described in, for example, English Paper Journal, VOL.E82-C, NO. 3, Yasuhiro KONISHI, et al., xe2x80x9cInterface Technologies for Memories and ASICs-Review and Future Directionxe2x80x9d, issued by the Institute of Electronics, Information and Communication Engineers, March 1999.
An SSTL-based memory system principally comprises a memory controller, signal wirings, connectors and memory modules mounted on a motherboard. The memory modules respectively have m memory chips provided on both surfaces of a module substrate. Data terminals of each individual memory chips are connected to their corresponding module data terminals in m units. Access control data terminals such as address terminals of the memory chips are connected to their corresponding module access control terminals. One-sided ends of the signal wirings are connected to their corresponding signal terminals of the memory controller, and the other ends thereof are terminated into a predetermined voltage. A plurality of memory modules are connected in parallel with their corresponding signal wirings through the connectors. Assuming now that the number of data terminals of each memory chip is defined as n and the number of the memory chips placed on the one side of each memory module is defined as m, the present memory system has mxc3x97n data signal wirings. The m memory chips placed on the one side of one memory module of plural memory modules are selected for one access according to a chip select signal generated by the memory controller. The ends or terminals of the signal wirings are connected to a terminal voltage through terminal resistors. Stub resistors for the memory controller are respectively series-connected to signal wirings for connecting the memory controller and the connectors.
Here, module wirings for connecting the module terminals of each memory module and the terminals of each memory chip constitute wirings which branch off from the signal wirings of the motherboard through the connectors. Stub resistors are placed in these module wirings. These stub resistors serve as matching loads for relaxing signal reflection developed in the signal wirings. Mismatching is generally developed in characteristic impedance at each wiring branch point. It is thus necessary to provide the stub resistors for relaxing the mismatching. Assuming that the characteristic impedance of each wiring is defined as Z0 and the characteristic impedance of each stub wiring is defined as Zs0, Zs-Z0/2 is suitable as the resistance value of each stub resistor. There is however the possibility that when the resistance value of the stub resistor increases, a voltage drop developed across the resistor will become great, thereby attenuating signal voltages such as addresses, data or the like and hence causing an error in a memory operation. When the resistance value of the stub resistor is less reduced to avoid the attenuation of each signal voltage for this season, there is the possibility that signal reflection will become obvious in reverse and hence a signal waveform will disturb, thereby causing a malfunction in the same manner as described above. As the operation is made fast to increase a signal frequency and each branch wiring against which countermeasures are to be taken by each stub resistor, becomes long, the disturbance of a signal waveform at a receiving end becomes great.
On the other hand, the present inventors have discussed, as another memory system, a type wherein a plurality of memory modules are series-connected via connectors to their corresponding signal wirings connected to a memory controller on a motherboard. The present inventors have discussed a configuration wherein on a memory module, a plurality of memory chips are connected by one-stroke writable wiring paths through module data signal wirings. Assuming that the number of data signal terminals of each memory element is defined as n in the present memory system, n module data signal wirings are provided therein regardless of the number m of memory elements placed on one side of each memory module, and one memory chip of the plural memory chips is selected for one access.
In another memory system referred above, all the memory modules are series-connected to their corresponding signal wirings on the motherboard, and the module signal wirings lying within the memory modules are series-connected to all the memory chips arranged in a line and are laid along the longitudinal direction of each memory module. Thus, the memory modules little form the branch wirings with respect to the signal wirings on the motherboard as in the case of the SSTL. A problem decreases that the disturbance of each waveform due to undesired signal reflection caused by the branch wirings occurs.
However, the present inventors have revealed that the length of the signal wiring increases, and the time necessary for the signal to propagate from the memory controller to the corresponding memory chip at the farthest end thereof becomes long, thus increasing a delay in access time.
Thus, a problem arises in that the module wirings of each memory module constitute the branch wirings on the memory system in the case of the SSTL type, whereby. the malfunction due to the signal reflection caused thereby occurs and the speeding up of the memory operation is limited. Since such branching for the signal wiring as developed in the SSTL little exists in the memory system of such a type that the plurality of memory modules are connected in series and the memory chips lying within the memory modules are connected in series, the branch wiring-based problem decreases. However, the present inventors have revealed the possibility that an increase in the length of the signal wiring lying within each memory module will cause a delay in access time and cannot cope with higher-speed access.
After the completion of the invention of the present application, the inventors of the present application have recognized the following examples known to date. Japanese Patent Application Laid-Open Nos. Hei 5(1993)-234355 and 6(1994)-150085 respectively have disclosed the invention wherein connectors are provided at both long-side portions of each memory module so that the plural memory modules can be connected in tandem. However, they do not disclose a wiring structure provided inside each memory module. Further, the present inventors have revealed that when the power, a clock signal, etc. are serially supplied, the supply thereof becomes instable. Japanese Patent Application Laid-Open No. Hei 7(1995)-334415 discloses a memory module having extended connectors which allow cascade connections of extended memory modules. Japanese Patent Application Laid-Open No. Hei 7(1995)-261892 discloses the invention wherein each of memory modules is provided with inlet connectors and outlet connectors, a memory bus on the memory module connects between them, and memory elements are connected in series with the memory bus, whereby undesired signal reflection is controlled. However, the first through third known examples merely provide the technology of cascade-connecting the memory modules to thereby configure the memory system. The fourth known example merely shows the system for connecting the plural memory elements to their corresponding memory bus on each memory module in series form. Any of the examples does not provide the conception leading to the invention of the present application.
The present invention aims to provide a memory system capable of controlling the disturbance of a signal waveform due to signal reflection to improve the reliability of signal transmission, increasing the stability of a memory operation, and restraining an increase in access time.
Further, the present invention aims to increase the speed for processing data by a computer system using a memory system.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be explained in brief as follows:
[1] A memory system includes a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to first and second module wirings. The memory connectors respectively have series paths (133, 134, 135) for serially connecting the first module wirings for a plurality of the mounted memory modules between the memory modules, and parallel paths (137, 138, 139) which are connected in parallel with the second module wirings for the plurality of mounted memory modules. The system board has first system wirings (107) connected to the series paths and second system wirings (108) each commonly connected to the parallel paths.
The first module wirings and the series paths constitute, for example, a form connected in series with the first system wirings to thereby constitute a memory access data bus connected to the controller, and the parallel paths constitute branch power wirings with respect to the second system wirings for supplying power.
As another aspect, the first module wirings and the series paths constitute, for example, a form connected in series with the first system wirings to thereby constitute clock wirings connected to the controller.
As a further aspect, the first module wirings and the series paths constitute a form connected in series with the first system wirings to thereby constitute command/address wirings connected to the controller.
The first module wirings (module data wirings) on each memory module constitute the memory access data bus in the memory system. Therefore, in a memory system in which a plurality of memory modules are made parallel, module data wirings for each memory module are connected in series form, and each individual module data wirings do not constitute branch wirings to first system wirings on a system board of the memory system. Thus, such signal reflection as caused by branching from a data bus like the first system wirings on the system board is not developed. Since the power or the like is supplied in parallel from the system board to each memory module through parallel paths, the supply of the power is stabilized. There is a possibility that when the power is supplied to the memory modules on a serial basis, for example, one memory module will produce power noise in the course thereof, thus causing its influence to propagate toward a subsequent stage. The above means do not produce such possibility, and hence a high degree of reliability can be ensured for a memory operation.
[2] A memory system as viewed from a further specific standpoint has a controller capable of controlling a memory, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules includes a plurality of memory chips having chip data terminals, a plurality of module data wirings individually provided in association with the respective chip data terminals of the plurality of memory chips, and module power wirings. The memory connectors respectively have series paths for serially connecting the module data wirings of a plurality of the mounted memory modules between the memory modules, and parallel paths which are connected in parallel with the module power wirings of the plurality of mounted memory modules. The system board has system data wirings connected to the series paths, and system power wirings each commonly connected to the parallel paths. The series paths constitute a memory access data bus together with the module data wirings of the memory modules mounted in the memory connectors, and the system data wirings. The parallel paths constitute power wirings together with the module power wirings of the memory modules mounted in the memory connectors, and the system power wirings.
Even according to the above means in a manner similar to the above, such signal reflection as caused by branching to a data bus on a motherboard of a memory system is not developed. Further, since the power or the like is supplied in parallel from the system board to each memory module through the parallel paths, the supply of the power is stabilized. In the memory system in addition to the above, parallel access for the number of bits corresponding to the width of the memory access data bus is assured for the memory module. Thus, the disturbance of each signal waveform due to the signal reflection is restrained while an increase in access time is being controlled, thereby making it possible to increase the reliability of signal transmission.
[3] A memory system as viewed from a still further standpoint includes a controller capable of controlling the operation of each memory, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings. The memory connectors respectively have series paths for serially connecting the module data wirings of the plurality of mounted memory modules between the memory modules. Further, the system board has system data wirings having one ends connected to the series paths, the other ends connected to terminal resistors, and intermediate portions connected to data terminals of the controller.
According to the above means in particular, since the data terminals of the controller are directly connected to their corresponding system data wirings, undesired branching from the system data wirings to the controller does not exist either in substance, and undesired signal reflection does not occur even in such portions.
If it is desired to positively manifest the fact that no undesired branching occurs in points where the system data wirings and the data terminals of the controller are connected, then their connecting points can be defined as having been included in one-stroke writable wiring paths. Alternatively, even if the branching is developed, no problem occurs if a wiring path length of each branching portion is set short in such a manner that the time necessary for a signal to ensure or assure a normal operation to go to and from a wiring path of the branching portion becomes shorter than a state transition time of the signal.
The terminal resistors may be separated from the system data wirings in response to a writing operation of each memory chip by the controller. Since terminal resistors on the memory controller side are supposed to be subjected to signal reflection read from a memory chip, low power consumption and an increase in signal amplitude can be achieved if the terminal resistors may be separated from the system data wirings in response to the writing operation of the memory chip.
[4] In the type of an output circuit and terminal resistors, a memory system includes a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips having chip data terminals respectively connected to module data wirings. The memory connectors respectively have series paths for serially connecting the module data wirings of the plurality of mounted memory modules between the memory modules. The system board has system data wirings connected to one ends of the series paths and connected to data terminals of the controller respectively. When, at this time, the memory chip has an open drain output circuit coupled to the chip data terminals, terminal resistors may be connected to the other ends of the series paths respectively without providing the system data wirings with their corresponding terminal resistors. When the controller has the open drain output circuit coupled to the data terminals thereof in reverse, the terminal resistors may be connected to the system data wirings respectively without providing the other ends of the series paths with the terminal resistors.
Since the open drain output circuit is high in output impedance and kept substantially constant in output impedance at its output operation, each terminal portion for allowing a signal outputted from the open drain output circuit to propagate is hard to be affected by undesired voltage reflection even if no terminal resistors are provided. It is thus possible to achieve low power consumption and an increase in signal amplitude.
[5] The memory system is particularly effective for application to, for example, a personal computer, a work station, or a data processing system requiring a large capacity memory, like a server. At this time, a data processor connected to the controller of the memory system and capable of obtaining access to each memory chip of the memory system is provided to configure a data processing system. Even when the frequency of the memory system is rendered high, a signal waveform is hard to get out of order owing to the above, and high-speed transmission is also allowed, thus contributing to an increase in the speed for processing data by a computer system.
[6] Terminal resistors are incorporated into the controller so as to be connectable to their corresponding system data terminals, and the electrical connections thereof to the system data wirings may be controlled according to an access mode or the like to each memory chip.